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Myths Programmers Believe about CPU Caches (2018)

(software.rajivprab.com)
149 points whack | 1 comments | 31 Oct 25 00:46 UTC | HN request time: 0.206s | source
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daemontus ◴[01 Nov 25 12:26 UTC] No.45781114[source]▶
I may be completely out of line here, but isn't the story on ARM very very different? I vaguely recall the whole point of having stuff like weak atomics being that on x86, those don't do anything, but on ARM they are essential for cache coherency and memory ordering? But then again, I may just be conflating memory ordering and coherency.
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1. jeffbee ◴[01 Nov 25 16:36 UTC] No.45783040[source]▶
Well, since this is a thread about how programmers use the wrong words to model how they think a CPU cache works, I think it bears mentioning that you've used "atomics" here to mean something irrelevant. It is not true that x86 atomics do nothing. Atomic instructions or, on x86, their prefix, make a naturally non-atomic operation such as a read-modify-write atomic. The ARM ISA actually lacked such a facility until ARMv8.1.

The instructions to which you refer are not atomics, but rather instructions that influence the ordering of loads and stores. x86 has total store ordering by design. On ARM, the program has to use LDAR/STLR to establish ordering.