←back to thread

149 points whack | 1 comments | | HN request time: 0s | source
Show context
groundzeros2015 ◴[] No.45780994[source]
Did this article share more than one myth?

The reason why programmers don’t believe in cache coherency is because they have experienced a closely related phenomena, memory reordering. This requires you to use a memory fence when accessing a shared value between multiples cores - as if they needed to synchronize.

replies(2): >>45781211 #>>45781571 #
Lwerewolf ◴[] No.45781211[source]
I'm pretty sure that most cases of x86 reordering issues are a matter of the compiler reordering things, which isn't (afaik) solved with just "volatile". Caveat - haven't dealt with this for at least over a year (multicore sync without using OS primitives in general).
replies(2): >>45781334 #>>45781345 #
1. nly ◴[] No.45781334[source]
x86 has a Total Store Order (TSO) memory model, which effectively means (in a mental model where only 1 shared memory operation happens at once and completes before the next) stores are queued but loads can be executed immediately even if stores are queued in the store buffer.

On a single core a load can be served from the store buffer (queue), but other cores can't see those stores yet, which is where all the inconsistencies come from.