←back to thread

Minecraft HDL, an HDL for Redstone

(github.com)
220 points sleepingreset | 1 comments | 30 Oct 25 18:59 UTC | HN request time: 0.207s | source
Show context
eirikbakke ◴[30 Oct 25 22:08 UTC] No.45765981[source]▶
In case anyone needs a minimal CPU implementation in 65 lines of Verilog: https://people.csail.mit.edu/ebakke/fic/ https://people.csail.mit.edu/ebakke/fic/code/Fic.v

(I wonder if it would convert cleanly to a redstone circuit...)

replies(1): >>45766079 #
1. lpribis ◴[30 Oct 25 22:18 UTC] No.45766079[source]▶
This compiler does not support sequential logic, meaning no flip flops/registers.