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unixfg ◴[] No.45754629[source]
Would this have been possible without PIO?
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codebje ◴[] No.45755273[source]
On a Pico? No - the PIOs replace other peripherals a µC might be able to use to achieve this sort of bitrate, so you'd not really have the tools you'd need to change GPIO pin states once every 3-4 CPU clock cycles.

In a sense the PIO is a bit 'cheaty' when claiming "bit-banging", because the PIO is the ultimate peripheral, programmable to be whatever you need. It's no mean feat to make the PIO do the sorts of things happening here, by any stretch, but "bit-banging" typically means using the CPU to work around the lack of a particular peripheral.

From that perspective, there's precious few µCs out there that could bit-bang 100MBit/s Ethernet - I'm no expert, but I _think_ that's a 125MHz IO clock, so if you want 4 CPU cycles per transition to load data and push it onto pins, you're looking for a 500MHz µC, and at those speeds you definitely have to worry about the bus characteristics, stalls, caching, and all those fun bits; it's not your old 8-bit CPU bit-banging a slow serial protocol over the parallel port any more.

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1. Neywiny ◴[] No.45755789[source]
Ehhhhh the picture shows a very short cable. You can most certainly find micros that can run 100Mb/s communication interfaces, though sure maybe not bitbanged. However, you really need a PHY and magnetics. MII is 25MHz which seems fine. GMII is 125 MHz SDR which is something. Honestly that would've been a cooler demo IMO than running 2 inches