Most active commenters

    ←back to thread

    263 points chaosprint | 14 comments | | HN request time: 0.016s | source | bottom
    Show context
    unixfg ◴[] No.45754629[source]
    Would this have been possible without PIO?
    replies(2): >>45754766 #>>45755273 #
    1. codebje ◴[] No.45755273[source]
    On a Pico? No - the PIOs replace other peripherals a µC might be able to use to achieve this sort of bitrate, so you'd not really have the tools you'd need to change GPIO pin states once every 3-4 CPU clock cycles.

    In a sense the PIO is a bit 'cheaty' when claiming "bit-banging", because the PIO is the ultimate peripheral, programmable to be whatever you need. It's no mean feat to make the PIO do the sorts of things happening here, by any stretch, but "bit-banging" typically means using the CPU to work around the lack of a particular peripheral.

    From that perspective, there's precious few µCs out there that could bit-bang 100MBit/s Ethernet - I'm no expert, but I _think_ that's a 125MHz IO clock, so if you want 4 CPU cycles per transition to load data and push it onto pins, you're looking for a 500MHz µC, and at those speeds you definitely have to worry about the bus characteristics, stalls, caching, and all those fun bits; it's not your old 8-bit CPU bit-banging a slow serial protocol over the parallel port any more.

    replies(5): >>45755402 #>>45755789 #>>45756583 #>>45757107 #>>45767713 #
    2. kfterrg67 ◴[] No.45755402[source]
    >"bit-banging" typically means using the CPU

    This is significant. It's using a hardware peripheral that is designed and intended for high frequency IO manipulation without CPU intervention. This isn't bit-banging, lest we start calling it "bit-banging" any time an FPGA or ASIC or even a microcontroller peripheral handles any kind of signalling.

    replies(1): >>45756116 #
    3. Neywiny ◴[] No.45755789[source]
    Ehhhhh the picture shows a very short cable. You can most certainly find micros that can run 100Mb/s communication interfaces, though sure maybe not bitbanged. However, you really need a PHY and magnetics. MII is 25MHz which seems fine. GMII is 125 MHz SDR which is something. Honestly that would've been a cooler demo IMO than running 2 inches
    4. ssl-3 ◴[] No.45756116[source]
    It's a programmable hardware peripheral runs compiled software to toggle pins in a way that is entirely defined by that software.

    Here, it runs software that allows it to talk 100mbps Ethernet.

    Someone else might use that same hardware peripheral to drive a display, or produce a PWM output, or whatever.

    The RP PIOs just run software. That software can bang bits.

    replies(2): >>45756174 #>>45756544 #
    5. picture ◴[] No.45756174{3}[source]
    Yeah but like FPGA fabric can also be programmed (sometimes by actual software like on Zynq or Stratix SoCs), would you call those bit banging too?
    replies(2): >>45756371 #>>45757712 #
    6. ssl-3 ◴[] No.45756371{4}[source]
    I don't have any hands-on experience with FPGAs. I only know about as much about FPGAs as I do about red herring.
    7. Dylan16807 ◴[] No.45756544{3}[source]
    Technically it's running software on the programmable I/O, but that software is just a loop of four outputs that advances when it gets a 1 bit and doesn't advance when it gets a 0 bit. It feels like the hardware that manages the buffer and turns it into a high speed serial stream is doing the more important work here.

    And the CPU that's actually deciding on the bits doesn't have to bang them with precise timing, it just has to put them into that buffer.

    8. rasz ◴[] No.45756583[source]
    >On a Pico? No

    but Yes on pico2 because RP2350 has separate fast serializer (HSTX) hardware block able to clock out at 2x the global clock (DDR). 320MHz OC results in 600Mbit output. Here example pumping out 175 MByte/s of data encoded as HDMI signal (3 lanes) without touching PIOs https://github.com/steve-m/hsdaoh-rp2350 to be used with $6 MS2130 USB 3.0 4k HDMI Video Capture dongle.

    replies(1): >>45756784 #
    9. codebje ◴[] No.45756784[source]
    They really are pretty awesome little ICs. Thanks for the interesting link!
    10. bitwize ◴[] No.45757107[source]
    It's why I call the Pico a "headless Amiga"—the PIOs are basically Coppers but for general I/O instead of tied to a display.

    I just wish the toolchain weren't so janky...

    replies(1): >>45761909 #
    11. KeplerBoy ◴[] No.45757712{4}[source]
    I feel most people would unless you use some Hard IP for the interface. Like you don't bit-bang PCIe when you feed a wide AXI stream at a few MHz into the PCIe block where it get's serialized and put onto the lanes at the signalling rate (multiple Gigahertz, depending on generation).
    12. pflanze ◴[] No.45761909[source]
    There's an independent reimplementation of the PIO assembler here: https://crates.io/crates/pio -- I haven't tried it so don't know how good.
    replies(1): >>45765020 #
    13. bitwize ◴[] No.45765020{3}[source]
    Intriguing, but I'm referring to the toolchain as a whole. Everything is done with CMake mumbo jumbo that is a pain to set up. For a computer this small and simple there should be a straightforward "compile .c to .o, link .o to flashable binary, flash binary" that any user can type in at the shell or put into a Makefile.
    14. lukeh ◴[] No.45767713[source]
    I think XMOS can do it (the ones without the GEMAC) but I'm not exactly sure how much hardware assistance they have.